Recently, ultra high density storage devices have been proposed using a three-dimensional (3D) stacked memory structure sometimes referred to as Bit Cost Scalable (BiCS) architecture. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. A memory opening is formed through the layers to define many memory layers simultaneously. A NAND string is then formed by filling the memory opening with appropriate materials. A straight NAND string extends in one memory opening, while a pipe- or U-shaped NAND string (p-BiCS) includes a pair of vertical columns of memory cells. Control gates of the memory cells may be provided by the conductive layers.
During formation of memory cells for the BiCS architecture, a memory film layer is deposited in each memory opening through an alternating stack of first material layers and second material layers. In order to protect vertical portions of the memory film layer during a subsequent anisotropic etch, a first semiconductor material layer may be conformally deposited on the contiguous memory film layer. The horizontal bottom portion of the memory film layer can be removed from each memory opening by an anisotropic etch to physically expose a first electrode or the substrate underlying the memory opening. A second semiconductor material layer is subsequently deposited directly on the first electrode or the substrate exposed in the memory opening and on the first semiconductor material layer. The first and second semiconductor material layers collectively function as a semiconductor channel of each memory cell in the NAND string.